CXA7000R Ver la hoja de datos (PDF) - Sony Semiconductor

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Fabricante

CXA7000R

LCD Driver

Sony Semiconductor 

CXA7000R

Pin

No.

Symbol

37 PRG_LV

38 SID_LV

I/O

Standard

voltage level

VDD

I 1.0 to 5.0V 37

38

GND

Equivalent circuit

29µ

50k

50k

Description

VCC

Precharge level setting.

Adjusts the SID_OUT and

SID_OUTX output potential.

PRG_LV is reflected when the

PRG input pin (Pin 60) is high,

and SID_LV is reflected when

PRG is low.

39 PRG

VDD

I

High: ≥2.0V

Low: ≤0.8V

39

GND

VDD

VCC

100k

10k

50µ

70µ

10µ

44 VREF_I

I

3.2V

44

GND

VDD

1k

280µ

33.3k

2k

45 VREF_O O

3.2V

46 F/H_CNT

High: ≥2.0V

I Low: ≤0.8V

Open: Low

47 DIRC

I

High: ≥2.0V

Low: ≤0.8V

20µ

GND

45

20k

12.4k

VDD

46

GND

50k

192

200k

VDD

50k

192

47

GND

Timing pulse input for switching

the Pin 36 output levels.

(See PRG_LV (Pin 37) and

SID_LV (Pin 38).)

Internal D/A converter reference

voltage input.

Normally connect directly to

VREF_O.

Reference voltage output.

Normally connect directly to

VREF_I, and connect to GND

through a 0.5 to 1.0µF capacitor.

SH_OUT output timing selection.

High: SH_OUT1 to SH_OUT3

and SH_OUT4 to SH_OUT6

are output at different timing.

Low: SH_OUT1 to SH_OUT6

are output at the same timing.

Scan direction setting.

High: output as a time series in

ascending order of output pin

symbol (in order from SH_OUT1

to SH_OUT6)

Low: output in descending order

–5–

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