Single mode
D_IN[9:0]
10bit
DD
D_IN1
DAC
D_IN2
D
DAC_O
S/H
CXA7000R
MCLK
D_IN[9:0] –1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLK
D_IN1
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
D_IN2
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
DAC_O
DIRC: H
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
F/H_CNT: L
SH3A_1_6
F/H_CNT : H
SH3B_1_3
SH3B_4_6
DIRC: L
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
F/H_CNT: L
SH3A_1_6
F/H_CNT: H
SH3B_1_3
SH3B_4_6
–1
0
1
CH1 to CH6 simultaneous output timing
CH1 to CH3 simultaneous output timing
CH4 to CH6 simultaneous output timing
– 13 –
CH1 to CH6 simultaneous output timing
CH1 to CH3 simultaneous output timing
CH4 to CH6 simultaneous output timing