Master/slave mode
D_IN[9:0]
10bit
DD
D_IN1
Selector
L
D
H
D
DAC
D_IN2
DAC_O
S/H
CXA7000R
MCLK
MCLK/2
STATUS
D_IN[9:0]
MCLK
D_IN1
D_IN2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
DAC_O
DIRC: H
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
F/H_CNT: L
SH3A_1_6
F/H_CNT: H
SH3B_1_3
SH3B_4_6
DIRC: L
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
F/H_CNT: L
SH3A_1_6
F/H_CNT: H
SH3B_1_3
SH3B_4_6
1
3
CH1 to CH6 simultaneous output timing
CH1 to CH3 simultaneous output timing
CH4 to CH6 simultaneous output timing
CH1 to CH6 simultaneous output timing
CH1 to CH3 simultaneous output timing
CH4 to CH6 simultaneous output timing
– 12 –