SST34HF1621 Ver la hoja de datos (PDF) - Silicon Storage Technology

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componentes Descripción

Fabricante

SST34HF1621

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory

Silicon Storage Technology 

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory

SST34HF1621 / SST34HF1641

Data Sheet

ADDRESSES AMSS-0

BES1#

TRCS

TAAS

TBES

BES2

OE#

UBS#, LBS#

DQ15-0

TBES

TBLZS

TOES

TOLZS

TBYLZS

TBYES

AMSS = Most Significant SRAM Address

FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM

TOHS

TBHZS

TOHZS

TBYHZS

DATA VALID

523 ILL F15.0

ADDRESSES AMSS-0

WE#

BES1#

TASTS

TWCS

TWPS

TAWS

TBWS

TWRS

BES2

TBWS

UBS#, LBS#

DQ15-8, DQ7-0

TODWS

NOTE 2

TBYWS

TDSS

TOEWS

TDHS

VALID DATA IN

NOTE 2

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low,

the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High,

the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse

polarity must not be applied.

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1

523 ILL F16.2

©2001 Silicon Storage Technology, Inc.

16

S71172-05-000 10/01 523

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