16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
ADDRESS A19-0
5555 2AAA
5555
5555
2AAA
BAX
BEF#
OE#
WE#
TWP
TBY
RY/BY#
DQ15-0
XXAA XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 12: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
TBR
VALID
523 ILL F10.4
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS A19-0
5555 2AAA
5555
5555
2AAA
SAX
BEF#
OE#
WE#
TWP
TBY
RY/BY#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 13: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
TBR
VALID
523 ILL F11.4
©2001 Silicon Storage Technology, Inc.
21
S71172-05-000 10/01 523