CXD3021R Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXD3021R Datasheet PDF : 161 Pages
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CXD3021R
Pin Symbol
No.
101 SSTP
102 DVSS5
103 DTS0
104 TES2
105 TES3
106 PWMI
107 DVDD5
108 VCOO
109 VCOI
110 TEST
111 PDO
112 VCKI
113 V16M
114 AVDD2
115 IGEN
116 AVSS2
117 ADIO
118 RFDC
119 CE
120 TE
I/O
I
I
I
I
I
O 1, 0
I
I
O 1, Z, 0
I
O 1, 0
I
O
I
I
I
Description
Disc innermost track detection signal input.
Digital GND.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Spindle motor external pin input.
Digital power supply.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
Connects the operational amplifier current source reference resistance.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
Notes) • The 32-bit/64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–8–
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