CXD3021 Ver la hoja de datos (PDF) - Sony Semiconductor
Número de pieza
componentes Descripción
Fabricante
CXD3021 Datasheet PDF : 161 Pages
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CXD3021R
Pin
No.
Symbol
I/O
Description
68 AVDD4
Analog power supply.
69 AVDD5
Master clock power supply.
70 XTLO O 1, 0 Master clock crystal oscillation circuit output.
71 XTLI
I
Master clock crystal oscillation circuit input.
72 AVSS5
Master clock GND.
73 AVSS3
Analog GND.
74 PWMLP O 1, Z, 0 Audio DAC PWM output. Left channel, forward phase.
75 PWMLN O 1, Z, 0 Audio DAC PWM output. Left channel, reversed phase.
76 AVDD3
Analog power supply.
77 DVDD4
Digital power supply.
78 SENS O 1, Z, 0 SENS output to CPU.
79 SCLK
I
SENS serial data readout clock input. Set to high when not used.
80 ATSK
I
Anti-shock pin. Set to low when not used.
81 DATA
I
Serial data input from CPU.
82 XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
83 CLOK I
Serial data transfer clock input from CPU.
84 DVSS4
Digital GND.
85 COUT I/O 1, 0 Track count signal I/O.
86 MIRR I/O 1, 0 Mirror signal I/O.
87 DFCT I/O 1, 0 Defect signal I/O.
88 FOK
I/O 1, 0 Focus OK signal I/O.
89 TESO O
Test pin. Leave this open.
90 FSW
O
1, Z, 0
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
91 AVSS6
Analog GND.
92 SAO
O
Sled filter DAC analog output.
93 TAO
O
Tracking filter DAC analog output.
94 FAO
O
Focus filter DAC analog output.
95 BSSD I
Constant current input for servo filter DAC analog output.
96 AVDD6
Analog power supply.
97 MON
O 1, 0 Spindle motor on/off control output.
98 MDP
O 1, Z, 0 Spindle motor servo control output.
99 MDS
O 1, Z, 0 Spindle motor servo control output.
100 LOCK
I/O 1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high. (See $3E.)
–7–
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