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CXD3003R

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

CXD3003R

Pin Symbol

I/O

No.

41 DA08 O 1, 0

42 DA07 O 1, 0

43 DVDD2

44 DA06 O 1, 0

45 DA05 O 1, 0

46 DA04 O 1, 0

47 DA03 O 1, 0

48 DA02 O 1, 0

49 DA01 O 1, 0

50 DVSS2

51 XTSL

I

52 MCKO O 1, 0

53 FSTI

I

55 FSTO O 1, 0

56 C4M

O 1, 0

57 C16M O 1, 0

58 DVDD3

59 MD2

I

60 DOUT O 1, 0

61 MUTE I

62 WFCK O 1, 0

63 SCOR O 1, 0

64 SBSO O 1, 0

65 EXCK I

66 SQSO O 1, 0

67 SQCK I

68 SCSY I

69 XRST

70 DTS2

75 DTS1

76 DTS0

77 XWO

78 DAS0

79 DAS1

80 DVSS3

81 AVSS4

82 AO2R

I

I

I

I

I

I

I

O 1, Z, 0

Description

DA08 output when PSSL = 1, GFS output when PSSL = 0.

DA07 output when PSSL = 1, RFCK output when PSSL = 0.

Digital power supply.

DA06 output when PSSL = 1, C2PO output when PSSL = 0.

DA05 output when PSSL = 1, XRAOF output when PSSL = 0.

DA04 output when PSSL = 1, MNT3 output when PSSL = 0.

DA03 output when PSSL = 1, MNT2 output when PSSL = 0.

DA02 output when PSSL = 1, MNT1 output when PSSL = 0.

DA01 output when PSSL = 1, MNT0 output when PSSL = 0.

Digital GND.

Crystal selection input.

Clock output. Inverted output of XTLI.

2/3 frequency division input for XTLI pin.

2/3 frequency division output for XTLI pin. Does not change with variable pitch.

1/4 frequency division output for XTLI pin. Changes with variable pitch.

16.9344MHz output. Changes simultaneously with variable pitch.

Digital power supply.

Digital Out on/off control (low = off, high = on).

Digital Out output.

Mute (low: off, high: on).

WFCK (Write Frame Clock) output.

Outputs a high signal when either subcode sync S0 or S1 is detected.

Sub P to W serial output.

SBSO readout clock input.

Sub Q 80-bit and PCM peak and level data 16-bit output.

SQSO readout clock input.

GRSCOR re-synchronization input. Normally low, re-syncronization is

executed when high.

System reset. Reset when low.

DAC test pin. Normally fixed to high.

DAC test pin. Normally fixed to high.

DAC test pin. Normally fixed to low.

DAC sync window open input. Normally high, window open when low.

DAC test pin. Normally fixed to high.

DAC test pin. Normally fixed to low.

Digital GND.

Analog GND.

Channel 2 DAC PWM output (reversed phase).

–6–

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