CXD2588R Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD2588R

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes.

The interface timing chart is shown below.

CLOK

750ns or more

CXD2588Q/R

DATA

D0 D1

XLAT

Registers

D18 D19 D20 D21 D22 D23

750ns or more

Valid

• The internal registers are initialized by a reset when XRST = 0.

Note) Be sure to set SQCK to high when XLAT is low.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7

8

9

A

B

C

D

E

Total bit length

8 bits

8 to 24 bits

8 bits

20 bits

28 bits

24 bits

28 bits

16 bits

8 bits

16 bits

20 bits

– 16 –

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