CL3128ATC100-10 Ver la hoja de datos (PDF) - Clear Logic
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CL3128ATC100-10 Datasheet PDF : 14 Pages
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CL3128A Laser Processed Logic Devices
AC Electrical Specifications cont.
External Timing Parameters
Symbol
Parameter
tPD1 Input to non-registered output
tPD2 I/O input to non-registered output
tSU Global clock setup time
tH
Global clock hold time
tCO1 Global clock to output delay
tCH Global clock high time
tCL Global clock low time
tASU Array clock setup time
tAH Array clock hold time
tACO1 Array clock to output delay
tACH Array clock high time
tACL Array clock low time
tCNT Minimum global clock period
fCNT Max. internal global clock frequency
tACNT Minimum array clock period
fACNT Max. internal array clock frequency
Conditions
CL = 35 pF
CL = 35 pF
CL = 35 pF
CL = 35 pF
Speed: -7
Min
Max
7.5
7.5
4.9
0.0
1.0
4.5
3.0
3.0
1.6
2.1
7.8
3.0
3.0
8.4
119.0
8.4
119.0
Speed: -10
Min
Max
10.0
Unit
ns
10.0
ns
6.6
ns
0.0
ns
1.0
5.9
ns
4.0
ns
4.0
ns
2.1
ns
3.4
ns
10.4
ns
4.0
ns
4.0
ns
11.2
ns
89.3
MHz
11.2
ns
89.3
MHz
3KA tbl 06A2
Page 9
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