S15(2012) Ver la hoja de datos (PDF) - Union Semiconductor, Inc.
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componentes Descripción
Fabricante
S15 Datasheet PDF : 5 Pages
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SM12/SM15
Electrical Characteristics (SM15)
PARAMETER
Reverse Stand-Off
Voltage
Reverse Breakdown
Voltage
Reverse Leakage
Current
Clamping Voltage
Peak Pulse Current
Junction Capacitance
Reverse dynamic
resistance
Forward dynamic
resistance
Reverse dynamic
resistance
Forward dynamic
resistance
SYMBOL
VRWM
VBR
IR
VC
IPP
CJ
Rdyn,rev
Rdyn,fwd
Rdyn,rev
Rdyn,fwd
CONDITIONS
It = 1mA
VRWM = 15V, T=25°C
IPP = 5.9A, tp = 8/20μS
tp = 8/20μs
Pin 1 to 3 and Pin 2 to 3,
VR = 0V, f = 1MHz
IPP<2A
IPP >2A
MIN TYP MAX
15
16.7
18.7
1
23
5.9
20 30
1.12
0.81
0.92
0.42
UNIT
V
V
μA
V
A
pF
Ω
Ω
Detailed Description
Device Connection Options
SM12/SM15 is designed to protect one bidirectional or two unidirectional data or I/O lines
operating at 12V/15V. Connection options are as follows: Bidirectional: Pin 1 is connected to the
data line and pin 2 is connected to ground (Since the device is symmetrical, these connections
may be reversed). The ground connection should be made directly to a ground plane. The path
length should be kept as short as possible to minimize parasitic inductance. Pin 3 is not connected.
Unidirectional: Data lines are connected to pin 1 and pin 2. Pin 3 is connected to ground. For best
results, this pin should be connected directly to a ground plane on the board. The path length
should be kept as short as possible to minimize parasitic inductance.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of fast rise-time transients such as ESD.
The following guidelines are recommended (Refer to application note SI99-01 for more detailed
information): Place the TVS near the input terminals or connectors to restrict transient coupling.
Minimize the path length between the TVS and the protected line. Minimize all conductive loops
including power and ground loops. The ESD transient return path to ground should be kept as
short as possible. Never run critical signals near board edges. Use ground planes whenever
possible.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte
tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads
is small compared to the solder paste volume that is placed on the land pattern of the PCB, the
reflow profile will be determined by the requirements of the solder paste. Therefore, these devices
are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other
lead-free compositions, matte tin does not have any added alloys that can cause degradation of the
solder joint.
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http://www.union-ic.com Rev.01 Jul.2012
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