AD7872 Ver la hoja de datos (PDF) - Analog Devices
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AD7872 Datasheet PDF : 24 Pages
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Data Sheet
AD7871/AD7872
TIMING CHARACTERISTICS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17.
Table 2.
Parameter1
t1
t2
t32
t4
t5
t62, 3
t72, 4
t8
t9
t10
t115
t126
t13
t14
t15
t16
t173
t18
t19
t20
Limit at TMIN, TMAX
(J, K, A, B Versions)
50
0
60
0
70
57
5
50
0
0
100
440
155
140
20
4
100
60
120
200
0
0
0
Limit at TMIN, TMAX
(T Version)
50
0
75
0
70
70
5
50
0
0
100
440
155
150
20
4
100
60
120
200
0
0
0
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
CONVST pulse width
CS to RD setup time (Mode 1)
RD pulse width
CS to RD hold time (Mode 1)
RD to INT delay
Data access time after RD
Bus relinquish time after RD
HBEN to RD setup time
HBEN to RD hold time
SSTRB to SCLK falling edge setup time
SCLK cycle time
SCLK to VALID DATA DELAY; CL = 35 pF
SCLK rising edge to SSTRB
Bus relinquish time after SCLK
CS to RD setup time (Mode 2)
CS to BUSY propagation delay
Data set up time prior to BUSY
CS to RD hold time (Mode 2)
HBEN to CS setup time
HBEN to CS hold time
1 Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The capacitance on all three outputs is 35 pF.
2 These timing specifications are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf =
5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3 t6 and t17 are measured with the load circuits of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of bus loading.
5 SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6 SDATA will drive higher capacitive loads, but this will add to t12 because it increases the external RC time constant (4.7 kΩ||CL) and therefore the time to reach 2.4 V.
Rev. E | Page 5 of 24
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