ADP3303(2017) Ver la hoja de datos (PDF) - Analog Devices
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ADP3303 Datasheet PDF : 16 Pages
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Data Sheet
THEORY OF OPERATION
The new anyCAP LDO ADP3303 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2, which is
varied to provide the available output voltage options. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
IN
OUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ADP3303
COMPENSATION
R1
CAPACITOR
ATTENUATION
(VBANDGAP /VOUT)
PTAT
gm
VOS
R3 D1
(a)
PTAT
CURRENT
R4
R2
GND
RLOAD
CLOAD
Figure 22. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed so that at equilibrium it produces a large,
temperature proportional input offset voltage that is repeatable
and very well controlled. The temperature-proportional offset
voltage is combined with the complementary diode voltage to
form a virtual band gap voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately,
this patented design makes it possible to control the loop with
only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility on
the tradeoff of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values are chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider to avoid the error resulting from base
current loading in conventional circuits.
ADP3303
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize due
to the uncertainty of load capacitance and resistance. Moreover,
the ESR value, required to keep conventional LDOs stable, changes
depending on load and temperature. These ESR limitations make
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
This is not true with the ADP3303 anyCAP LDO. The ADP3303
can be used with virtually any capacitor, with no constraint on
the minimum ESR. The innovative design allows the circuit to
be stable with just a small 0.47 µF capacitor on the output.
Additional advantages of the pole splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive ±1.4%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit, thermal
shutdown, and noise reduction. Compared to standard solutions
that give warning after the output loses regulation, the ADP3303
provides improved system performance by enabling the ERR
pin to give warning before the device loses regulation.
As the temperature of the chip rises above 165°C, the circuit
activates a soft thermal shutdown, indicated by a signal low on
the ERR pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main divider
network (a) is made available at the noise reduction (NR) pin,
which can be bypassed with a small capacitor (10 nF to 100 nF).
Rev. D | Page 9 of 16
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