TDA7309D013TR Ver la hoja de datos (PDF) - STMicroelectronics

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TDA7309D013TR

DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS

STMicroelectronics 

Figure 17. Acknowledge on the I2CBUS

TDA7309

SCL

1

2

3

7

8

9

SDA

START

MSB

D99AU1033

ACKNOWLEDGMENT

FROM RECEIVER

Table 6. SDA, SCL I2CBUS Timing

Symbol

Parameter

Min.

fSCL

SCL clock frequency

0

tBUF

Bus free time between a STOP and START condition

1.3

tHD:STA Hold time (repeated) START condition. After this period, the first 0.6

clock pulse is generated

tLOW

LOW period of the SCL clock

1.3

tHIGH

tSU:STA

tHD:DA

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

0.6

0.6

0.300

tSU:DAT Data set-up time

100

tR

Rise time of both SDA and SCL signals

20

tF

Fall time of both SDA and SCL signals

20

tSU:STO Set-up time for STOP condition

0.6

All values referred to VIH min. and VIL max. levels

(*) Must be guaranteed by the I2C BUS master.

Figure 18. Definition of Timing on the I2C-bus

Typ.

Max. Unit

400 kHz

µs

µs

µs

µs

µs

µs

ns

300 ns (*)

300 ns (*)

µs

SDA

tBUF

tR tF

SCL

tLOW

P

S tHD;STA

P = STOP

S = START

tHD;DAT

tHIGH

tF

tHD;STA

tSP tSU;STO

tSU;STA

tSU;DAT

Sr

P

D95AU314

7/14

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