MP44010(2012) Ver la hoja de datos (PDF) - Monolithic Power Systems
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MP44010 Datasheet PDF : 14 Pages
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MP44010 – BOUNDARY MODE PFC CONTROLLER
OPERATION
The MP44010 is a boundary conduction mode
PFC controller which is optimized for the PFC
pre-regulator up to 300W and fully complies with
the IEC1000-3-2 specification.
Output Voltage Regulation
The output voltage is sensed at the FB pin
through a resistor divider from output voltage to
ground. The accurate on-chip reference voltage
and the high performance error amplifier regulate
the output voltage accurately.
Over-Voltage Protection (OVP)
The MP44010 offers two stages of over-voltage
protection: dynamic over-voltage protection and
static over-voltage protection. With two-stage
protection, the circuit can operate reliably.
The MP44010 achieves OVP by monitoring the
current flow through the COMP pin.
At steady-state operation, the current flow
through high-side feedback resistor R9 and low-
side feedback resistor R10 is:
IR9
=
VO − VFB
R9
= IR10
=
VFB
R10
If there is an abrupt rise on the output (ΔVO), and
the compensation network connected between
FB pin and COMP pin takes time to achieve high
power factor (PF) due to the long RC time
constant. The voltage on FB pin will still be kept
at the reference value. The current through R10
remains equal to VFB/R10, but the current through
R9 will become:
IR' 9
=
VO
+
ΔVO
R9
− VFB
This current has to flow into the COMP pin. At
the same time, this current is monitored inside
the chip. If it rises to 35µA, the output voltage of
the multiplier will be forced to decrease and the
energy delivering to output will be reduced. If this
current continues to rise to about 40µA, the
dynamic OVP could be triggered. Consequently,
the gate driver is blocked to turn off the external
power MOSFET and the device enters an idle
state. This state is maintained until the current
falls below 10µA, the point at which, the internal
starter will be re-enabled and allows the
switching to restart.
When the load is very light, the output voltage
tends to stay steadily above the nominal value. In
this condition, the error amplifier output will
saturate low. When the error amplifier output is
lower than 2.2V, static OVP will be triggered.
Consequently, the gate driver will be blocked to
turn off the external power MOSFET and the
device enters an idle state. Normal operation is
resumed once the error amplifier output goes
back into the regulated region.
UVLO
Driver
Multiplier
Overvoltage
detection
-
+
2.5V
MULT
COMP
GATE
Vo
IR9
R9
FB
I R10
R10
Figure 2—OVP Detector Block
Disable Function
The MP44010 can be disabled by pulling the
zero current sensing (ZCS) pin lower than
190mV. This can help to further reduce quiescent
current when the PFC pre-regulator needs to be
shutdown. After releasing the ZCS pin, it will stay
at lower clamp voltage when there is no external
voltage from auxiliary winding.
Boundary Conduction Mode
Vaux
ZCS
2.1V
1.35V
Disable
-
+
starter
SQ
R
Driver
GATE
Figure 3—ZCS, Triggering and Disable Block
MP44010 Rev. 1.11
www.MonolithicPower.com
9
10/17/2012
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© 2012 MPS. All Rights Reserved.
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