74ABT841 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74ABT841 Datasheet PDF : 15 Pages
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NXP Semiconductors
74ABT841
10-bit bus interface latch; 3-state
6. Functional description
Table 3. Function table[1]
Input
OE
LE
nD
L
H
L
L
H
H
L
l
L
h
H
X
X
L
L
X
Output
Q0 to Q9
L
H
L
H
Z
NC
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
= HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Operating mode
transparent
latched
high-impedance
hold
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
input clamping current
IOK
output clamping current
IO
output current
Tj
junction temperature
Tstg
storage temperature
output in OFF-state or HIGH-state
VI < 0 V
VO < 0 V
output in LOW-state
Min
0.5
[1] 1.2
[1] 0.5
18
50
-
[2] -
65
Max Unit
+7.0 V
+7.0 V
+5.5 V
-
mA
-
mA
128
mA
150
C
+150 C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
74ABT841
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 November 2011
© NXP B.V. 2011. All rights reserved.
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