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Fabricante

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

NXP Semiconductors. 

Philips Semiconductors

16-bit transceiver/register with dual enable; 3-state

Product specification

74ALVCH16652

FEATURES

• In accordance with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTE™ flow-through pin-out architecture

• Low inductance, multiple supply and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold

• Output drive capability 50 Ω transmission lines at 85 °C

• Current drive ±24 mA at 3.0 V.

DESCRIPTION

The 74ALVCH16652 consists of 16 non-inverting bus

transceiver circuits with 3-state outputs, D-type flip-flops

and control circuitry arranged for multiplexed transmission

of data directly from the data bus or from the internal

storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the

internal registers, at the appropriate clock inputs

(nCPAB or nCPBA) regardless of the select inputs (nSAB

and nSBA) or output enable (nOEAB and nOEBA) control

inputs.

Depending on the select inputs nSAB and nSBA data can

directly go from input to output (real-time mode) or data

can be controlled by the clock (storage mode), when OE

inputs permit this operating mode.

The output enable inputs nOEAB and nOEBA determine the

operation mode of the transceiver. When nOEAB is LOW,

no data transmission from nBn to nAn is possible and when

nOEBA is HIGH, no data transmission from nBn to nAn is

possible.

When nSAB and nSBA are in the real-time transfer mode, it

is also possible to store data without using the internal

D-type flip-flops by simultaneously enabling nOEAB and

nOEBA. In this configuration each output reinforces its

input.

Active bus hold circuitry is provided to hold unused or

floating data inputs at a valid logic level.

QUICK REFERENCE DATA

Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns.

SYMBOL

PARAMETER

tPHL/tPLH

fmax

CI

CPD

propagation delay nAn, nBn to nBn, nAn

maximum clock frequency

input capacitance

power dissipation capacitance per latch

CONDITIONS

CL = 50 pF; VCC = 3.3 V

notes 1 and 2

outputs enabled

outputs disabled

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

CL = output load capacitance in pF;

fo = output frequency in MHz;

VCC = supply voltage in Volts;

Σ (CL × VCC2 × fo) = sum of outputs.

2. The condition is VI = GND to VCC.

TYPICAL

2.6

350

4.0

UNIT

ns

MHz

pF

22

pF

4.0

pF

1999 Nov 23

2

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