74ALVCH16823DGG Ver la hoja de datos (PDF) - NXP Semiconductors.
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74ALVCH16823DGG
NXP Semiconductors.
74ALVCH16823DGG Datasheet PDF : 18 Pages
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Nexperia
74ALVCH16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
7 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
input clamping current
IOK
output clamping current
IO(sink/source) output sink or source current
ICC
supply current
IGND
ground current
Tstg
storage temperature
Ptot
total power dissipation
For control pins
For data inputs
−0.5
[1]
−0.5
[1]
−0.5
[1]
−0.5
VI < 0 V
−50
VO > VCC or VO < 0 V
-
VO = 0 V to VCC
-
-
−100
−65
Tamb = −40 °C to +125 °C
[2]
-
+4.6
V
+5.5
V
VCC + 0.5 V
VCC + 0.5 V
-
mA
±50
mA
±50
mA
100
mA
-
mA
+150
°C
600
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.
8 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC
supply voltage
2.5 V range for maximum speed
performance at 30 pF output load
3.3 V range for maximum speed
performance at 50 pF output load
for low-voltage applications
VI
input voltage
for data inputs
for control inputs
VO
Tamb
Δt/ΔV
output voltage
ambient temperature
input transition rise and fall rate
in free air
VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
Min
Max Unit
2.3
2.7
V
3.0
3.6
V
1.2
3.6
V
0
VCC
V
0
5.5
V
0
VCC
V
-40
+85 °C
-
20
ns/V
-
10
ns/V
74ALVCH16823
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 February 2018
© Nexperia B.V. 2018. All rights reserved.
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