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74ALVCH16823 Datasheet PDF : 18 Pages
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Nexperia
74ALVCH16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
3 Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVCH16823DGG −40 °C to +85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
4 Functional diagram
28 2MR
1 1MR
54 1D0
52 1D1
51 1D2
49 1D3
48 1D4
47 1D5
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
38 2D3
37 2D4
36 2D5
34 2D6
33 2D7
31 2D8
56 1CP
29 2CP
Figure 1. Logic symbol
1OE 2
2OE 27
1Q0 3
1Q1 5
1Q2 6
1Q3 8
1Q4 9
1Q5 10
1Q6 12
1Q7 13
1Q8 14
2Q0 15
2Q1 16
2Q2 17
2Q3 19
2Q4 20
2Q5 21
2Q6 23
2Q7 24
2Q8 26
2CE 30
1CE 55
aaa-028141
VCC
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
2
1
55
56
27
28
30
29
EN1
R2
G3
3C4
EN5
R6
G7
7C8
1D0 54
1D1 52
1D2 51
1D3 49
1D4 48
1D5 47
1D6 45
1D7 44
1D8 43
2D0 42
2D1 41
2D2 40
2D3 38
2D4 37
2D5 36
2D6 34
2D7 33
2D8 31
4D 1,2
8D 5,6
3 1Q0
5 1Q1
6 1Q2
8 1Q3
9 1Q4
10 1Q5
12 1Q6
13 1Q7
14 1Q8
15 2Q0
16 2Q1
17 2Q2
19 2Q3
20 2Q4
21 2Q5
23 2Q6
24 2Q7
26 2Q8
001aad242
Figure 2. IEC logic symbol
data input
to internal circuit
Figure 3. Bushold circuit (one data input)
001aad245
74ALVCH16823
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 February 2018
© Nexperia B.V. 2018. All rights reserved.
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