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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

NXP Semiconductors. 

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

10.1 Waveforms and test circuit

1/ fmax

VI

nCP input

VM

VM

GND

VOH

tW

t PHL

t PLH

nQn output

VM

VOL

001aaa256

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 6. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock (nCP)

frequency

VI

input nDn,

nCE

VM

VM

VM

VM

GND

tsu(H) th(H)

tsu(L) th(L)

VI

input nCP

VM

VM

GND

001aad 401

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 7. Data set-up and hold times for the nDn or nCE input to the nCP input

VI

input nMR

VM

VM

GND

VI

t WL

t rec

input nCP

VM

GND

VOH

t PHL

output nQn

VM

VOL

001aad 400

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 8. Master reset (nMR) pulse width, master reset (nMR) to output (nQn) propagation delay and master reset

(nMR) to clock (nCP) recovery time

74ALVCH16823

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 1 February 2018

© Nexperia B.V. 2018. All rights reserved.

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