74ALVCH16823DGG Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Fabricante

74ALVCH16823DGG

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

NXP Semiconductors. 

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol

trec

fmax

CPD

Parameter

recovery time

maximum frequency

power dissipation

capacitance

Conditions

nMR to nCP; see Figure 8

VCC = 1.8 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

nCP; see Figure 6

VCC = 1.8 V

VCC = 2.3 V to 2.7 V

VCC = 2.7 V

VCC = 3.0 V to 3.6 V

per latch; VI = GND to VCC

outputs enabled

outputs disabled

[1] Typical values are measured at Tamb = 25 °C

Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V.

Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V.

[2] tpd is the same as tPLH and tPHL.

[3] ten is the same as tPZL and tPZH.

[4] tdis is the same as tPLZ and tPHZ.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

∑(CL × VCC2 × fo) = sum of outputs.

Min

0.8

1.0

0.8

1.0

125

150

150

200

[5]

-

-

Typ[1]

0.2

0.3

0.1

0.2

250

300

300

350

16

10

Max Unit

-

ns

-

ns

-

ns

-

ns

-

MHz

-

MHz

-

MHz

-

MHz

-

pF

-

pF

74ALVCH16823

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 1 February 2018

© Nexperia B.V. 2018. All rights reserved.

10 / 18

Share Link: