74HCT107D Ver la hoja de datos (PDF) - NXP Semiconductors.
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Fabricante
74HCT107D Datasheet PDF : 18 Pages
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Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
9,
W:
QHJDWLYH
SXOVH
90
9
WI
9,
SRVLWLYH
SXOVH
WU
90
9
W:
90
WU
WI
90
9,
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9&&
92
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57
9&&
5/ 6
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RSHQ
DDG
Fig 7.
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Test circuit for measuring switching times
Table 9. Test data
Type
Input
74HC107
74HCT107
VI
tr, tf
VCC
6 ns
3V
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
RL
1 k
1 k
S1 position
tPHL, tPLH
open
open
tPZH, tPHZ
GND
GND
tPZL, tPLZ
VCC
VCC
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© Nexperia B.V. 2017. All rights reserved
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