BUK100-50DL Ver la hoja de datos (PDF) - Philips Electronics
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BUK100-50DL Datasheet PDF : 10 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK100-50DL
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
Ld
Internal drain inductance
Ld
Internal drain inductance
Ls
Internal source inductance
CONDITIONS
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
MIN. TYP. MAX. UNIT
-
3.5
-
nH
-
4.5
-
nH
-
7.5
-
nH
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised limiting power dissipation.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.3. Normalised continuous drain current.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
ID & IDM / A
100
RDS(ON) = VDS/ID
10
DC
1
BUK100-50DL
tp =
100 us
1 ms
10 ms
100 ms
Overload protection characteristics not shown
0.1
1
10
100
VDS / V
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth / (K/W)
10
BUK100-50DL
D=
0.5
1
0.2
0.1
0.05
0.1 0.02
PD
tp
D=
tp
T
0
0.01
1E-07
1E-05
1E-03
t/s
T
t
1E-01
Fig.5. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1E+01
November 1996
5
Rev 1.200
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