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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

MII Management (MIIM) Interface

The KSZ9031RNX supports the IEEE 802.3 MII Management interface, also known as the Management Data Input/

Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9031RNX.

An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details

about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows an external controller

to communicate with one or more KSZ9031RNX devices. Each KSZ9031RNX device is assigned a unique PHY

address between 0h and 7h by the PHYAD[2:0] strapping pins.

• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect

access to MMD addresses and registers. See the Register Map section.

PHY Address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address, which

allows for a single write command to simultaneously program an identical PHY register for two or more PHY devices (for

example, using PHY Address 0h to set Register 0h to a value of 0x1940 to set Bit [11] to a value of one to enable

software power-down). Instead, separate write commands are used to program each PHY device.

Table 8 shows the MII Management frame format for the KSZ9031RNX.

Table 8. MII Management Frame Format for the KSZ9031RNX

Preamble

Start of

Frame

Read/Write

OP Code

PHY

Address

Bits [4:0]

REG

Address

Bits [4:0]

TA

Data

Bits [15:0]

Idle

Read 32 1’s

01

10

00AAA

RRRRR

Z0

DDDDDDDD_DDDDDDDD

Z

Write 32 1’s

01

01

00AAA

RRRRR

10

DDDDDDDD_DDDDDDDD

Z

May 14, 2015

28

Revision 2.2

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