KSZ9031RNX Ver la hoja de datos (PDF) - Micrel

Número de pieza

componentes Descripción

Fabricante

KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Table 6. Absolute Delay for 4-Bit Pad Skew Setting

Pad Skew (value)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Delay (ns)

–0.42

–0.36

–0.30

–0.24

–0.18

–0.12

–0.06

No delay adjustment (default value)

+0.06

+0.12

+0.18

+0.24

+0.30

+0.36

+0.42

+0.48

When computing the RGMII timing relationships, delays along the entire data path must be aggregated to determine the

total delay to be used for comparison between RGMII pins within their respective timing group. For the transmit data path,

total delay includes MAC output delay, MAC-to-PHY PCB routing delay, and PHY (KSZ9031RNX) input delay and skew

setting (if any). For the receive data path, the total delay includes PHY (KSZ9031RNX) output delay, PHY-to-MAC PCB

routing delay, and MAC input delay and skew setting (if any).

As the default, after power-up or reset, the KSZ9031RNX RGMII timing conforms to the timing requirements in the RGMII

Version 2.0 Specification for internal PHY chip delay.

For the transmit path (MAC to KSZ9031RNX), the KSZ9031RNX does not add any delay locally at its GTX_CLK, TX_EN

and TXD[3:0] input pins, and expects the GTX_CLK delay to be provided on-chip by the MAC. If MAC does not provide

any delay or insufficient delay for the GTX_CLK, the KSZ9031RNX has pad skew registers that can provide up to 1.38ns

on-chip delay.

For the receive path (KSZ9031RNX to MAC), the KSZ9031RNX adds 1.2ns typical delay to the RX_CLK output pin with

respect to RX_DV and RXD[3:0] output pins. If necessary, the KSZ9031RNX has pad skew registers that can adjust the

RX_CLK on-chip delay up to 2.58ns from the 1.2ns default delay.

The above default RGMII timings imply:

• RX_CLK clock skew is set by the KSZ9031RNX default register settings.

• GTX_CLK clock skew is provided by the MAC.

• No PCB delay is required for GTX_CLK and RX_CLK clocks.

The following examples show how to read/write to MMD Address 2h, Register 8h for the RGMII GTX_CLK and RX_CLK

skew settings. MMD register access is through the direct portal Registers Dh and Eh. For more programming details, refer

to the MMD Registers – Descriptions section.

• Read back value of MMD Address 2h, Register 8h.

- Write Register 0xD = 0x0002

// Select MMD Device Address 2h

- Write Register 0xE = 0x0008

// Select Register 8h of MMD Device Address 2h

- Write Register 0xD = 0x4002

// Select register data for MMD Device Address 2h, Register 8h

- Read Register 0xE

// Read value of MMD Device Address 2h, Register 8h

May 14, 2015

26

Revision 2.2

Share Link: