KSZ9031RNX(2012) Ver la hoja de datos (PDF) - Micrel

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componentes Descripción

Fabricante

KSZ9031RNX
(Rev.:2012)

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

List of Figures

Figure 1. KSZ9031RNX Block Diagram ............................................................................................................................... 16

Figure 2. KSZ9031RNX 1000Base-T Transceiver Block Diagram – Single Channel.......................................................... 18

Figure 3. Auto-Negotiation Flow Chart................................................................................................................................. 21

Figure 4. KSZ9031RNX RGMII Interface ............................................................................................................................. 23

Figure 5. Local (Digital) Loopback ....................................................................................................................................... 29

Figure 6. Remote (Analog) Loopback .................................................................................................................................. 30

Figure 7. LPI Mode (Refresh Transmissions and Quiet Periods) ........................................................................................ 33

Figure 8. LPI Transition – RGMII (1000Mbps) Transmit ...................................................................................................... 33

Figure 9. LPI Transition – RGMII (100Mbps) Transmit ........................................................................................................ 34

Figure 10. LPI Transition – RGMII (1000Mbps) Receive ..................................................................................................... 35

Figure 11. LPI Transition – RGMII (100Mbps) Receive ....................................................................................................... 35

Figure 12. RGMII v2.0 Specification (Figure 3 – Multiplexing and Timing Diagram)........................................................... 65

Figure 13. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 66

Figure 14. MDC/MDIO Timing.............................................................................................................................................. 67

Figure 15. Power-Up/Power-Down/Reset Timing ................................................................................................................ 68

Figure 16. Recommended Reset Circuit .............................................................................................................................. 69

Figure 17. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 69

Figure 18. Reference Circuits for LED Strapping Pins......................................................................................................... 70

Figure 19. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 71

Figure 20. Typical Gigabit Magnetic Interface Circuit .......................................................................................................... 72

Figure 21. Recommended Land Pattern, 48-Pin (7mm x 7mm) QFN ................................................................................. 74

October 2012

7

M9999-103112-1.0

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