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AR9271 Datasheet PDF : 152 Pages
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6.8.1 Reset the MAC AHB/APB Interface
(H_RC) .......................................... 94
6.8.2 EEPROM Control
(H_EEPROM_CTRL) .................. 94
6.8.3 MAC Silicon Revision ID
(H_SREV_ID) ............................... 94
6.8.4 AHB Mode (AHB_MODE) ........ 95
6.8.5 Interrupt Cause Clear
(H_INTR_CAUSE_CLR) ............ 96
6.8.6 Synchronous Interrupt Cause
(H_INTR_SYNC_CAUS) ........... 96
6.8.7 Synchronous Interrupt Enable
(H_INTR_SYNC_ENAB) ........... 97
6.8.8 Asynchronous Interrupt Mask
(H_INTR_ASYN_MASK) .......... 97
6.8.9 Synchronous Interrupt Mask
(H_INTR_SYN_MASK) ............. 97
6.8.10 Asynchronous Interrupt Cause
(H_INTR_ASYN_CAUS) ........... 97
6.8.11 Asynchronous Interrupt Enable
(H_INTR_ASYN_ENAB) ........... 97
6.8.12 GPIO Input and Output
(H_GPIO_IN_OUT) .................... 98
6.8.13 GPIO Output Enable Bits
(H_GPIO_OE_BITS) ................... 98
6.8.14 GPIO Interrupt Polarity
(H_GPIO_IRQ_POLAR) ............ 99
6.8.15 GPIO Input Enable and Value
(H_GP_INPT_EN_VAL) ............ 99
6.8.16 GPIO Input MUX1
(H_GP_INPT_MUX1) ................. 99
6.8.17 GPIO Input MUX2
(H_GP_INPT_MUX2) ............... 100
6.8.18 GPIO Output MUX1
(H_GP_OUTPT_MUX1) .......... 100
6.8.19 GPIO Output MUX2
(H_GP_OUTPT_MUX2) .......... 100
6.8.20 Input Values (H_INPUT_STATE)
101
6.8.21 EEPROM Status and Read Data
(H_EEP_STS_DATA) ............... 102
6.8.22 RFSilent-Related Registers
(H_RFSILENT) .......................... 102
6.8.23 GPIO Pull-Up/Pull-Down
(H_GPIO_PDPU) ...................... 103
6.8.24 GPIO Drive Strength
(H_GPIO_DS) ............................ 103
6.8.25 AHB Burst Mode
(MAC_AHB_BURST_MODE) 104
6.9 RTC Interface Registers ...................... 104
6.9.1 RTC Reset and Force Sleep and
Force Wakeup (RTC_RESET) . 105
6.9.2 RTC Sleep Status (RTC_STATUS)
105
6.9.3 RTC Force Derived RTC and Bypass
Derived RTC (RTC_DERIVED) 105
6.9.4 RTC Force Wake
(RTC_FORCE_WAKE) ............ 105
6.9.5 RTC Interrupt Cause
(RTC_INT_CAUSE) .................. 106
6.9.6 RTC Interrupt Cause Clear
(RTC_CAUSE_CLR) ................. 106
6.9.7 RTC Interrupt Enable
(RTC_INT_ENABLE) ............... 107
6.9.8 RTC Interrupt Mask
(RTC_INT_MASK) ................... 107
6.10 MAC Interface Registers .................... 108
6.10.1 MAC Sleep Status (MAC_SLEEP)
108
6.10.2 MAC LED Control (MAC_LED) ..
108
6.11 MAC PCU Registers ........................... 109
6.11.1 STA Address Lower 32 Bits
(MAC_PCU_STA_ADDR_L32) 111
6.11.2 STA Address Upper 16 Bits
(MAC_PCU_STA_ADDR_U16) 111
6.11.3 BSSID Lower 32 Bits
(MAC_PCU_BSSID_L32) ......... 112
6.11.4 BSSID Upper 16 Bits
(MAC_PCU_BSSID_U16) ........ 112
6.11.5 Beacon RSSI Average
(MAC_PCU_BCN_RSSI_AVE) 112
6.11.6 ACK and CTS Timeout
(MAC_PCU_ACK_CTS_TIMEOUT
) .................................................... 113
6.11.7 Beacon RSSI Control
(MAC_PCU_BCN_RSSI_CTL) 113
6.11.8 Ms Counter and Rx/Tx Latency
(MAC_PCU_USEC_LATENCY) ..
113
6.11.9 Reset TSF
(MAC_PCU_RESET_TSF) ....... 114
6.11.10 Maximum CFP Duration
(MAC_PCU_MAX_CFP_DUR) 114
6.11.11 Rx Filter
6 • AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs
6 • November 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
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