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AR9271 Datasheet PDF : 152 Pages
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Table of Contents
General Description ........................................ 1
Features ............................................................ 1
AR9271 System Block Diagram .................... 1
1 Pin Descriptions ............................ 9
2 Functional Description ............... 13
2.1 Overview ................................................. 13
2.1.1 Configuration Block ................... 13
2.1.2 AR9271 Address MAP ............... 13
2.1.3 Serial EEPROM Interface ........... 14
2.1.4 EEPROM Auto-Sizing Mechanism
14
2.1.5 EEPROM Read/Write Protection
Mechanism ................................... 14
2.2 Reset ......................................................... 14
2.3 GPIO ........................................................ 14
2.4 LED .......................................................... 14
2.5 USB Host Interface ................................. 14
2.6 The CPU Block ....................................... 15
2.6.1 The CPU ....................................... 15
2.6.2 Memory Controller and the AHB
Arbiter .......................................... 15
2.6.3 Internal Memories ...................... 15
2.6.4 The AHB Proc .............................. 15
3 Medium Access Control (MAC) 17
3.1 Overview ................................................. 17
3.2 Descriptor ................................................ 17
3.3 Descriptor Format .................................. 18
3.4 Queue Control Unit (QCU) .................. 32
3.4.1 DCF Control Unit (DCU) ........... 32
3.5 Protocol Control Unit (PCU) ................ 32
4 Digital PHY Block ....................... 33
4.1 Overview ................................................. 33
4.2 802.11n Mode .......................................... 33
4.2.1 Transmitter (Tx) .......................... 33
4.2.2 Receiver (Rx) ............................... 33
4.3 802.11b/g Legacy Mode ........................ 34
4.3.1 Transmitter .................................. 34
4.3.2 Receiver ........................................ 34
5 Radio Block ...................................35
5.1 Receiver (Rx) Block ................................ 35
5.2 Transmitter (Tx) Block .......................... 35
5.3 Synthesizer (SYNTH) Block ................. 36
5.4 Bias/Control (BIAS) Block ................... 36
6 Register Descriptions ..................37
CPU Block 37
6.1 USB Controller PIO Registers .............. 37
6.1.1 Endpoint Data Port Register
(EP0_DB) ...................................... 38
6.1.2 USB Data Width Control Register
(UC_CTL) .................................... 38
6.1.3 USB DMA Control Register
(UD_CTRL) .................................. 38
6.1.4 USB Upstream Stream Mode MAX
Aggregate Register (REG_APKT)
39
6.1.5 USB Upload Time Control ........ 40
6.1.6 USB DMA Reset Control Register
40
6.1.7 USB Controller Wake Up .......... 40
6.1.8 USB Clock Status Register
(US_CLK_STS) ............................ 40
6.2 Reset/Clock Control Register .............. 41
6.2.1 General Purpose Timer Register
(RST_GENERAL_TIMER) ......... 41
6.2.2 General Purpose Timer Reload
Register
(RST_GENERAL_TIMER_RELOA
D) .................................................. 41
6.2.3 Watchdog Timer Control Register
(RST_WATCHDOG_TIMER_CON
TROL) ........................................... 42
6.2.4 Watchdog Timer Register
(RST_WATCHDOG_TIMER) ... 42
6.2.5 Reset Register (RST_RESET ..... ) 42
6.2.6 Bootstrap Values .............................
(RST_BOOTSTRAP) ................... 42
6.2.7 Watchdog Timer Interrupt
(RST_WATCHDOG_INT) ......... 43
6.2.8 General Timer Interrupt
(RST_GENERAL_TIMER_INT) 43
6.2.9 Clock Control Register ............... 43
6.2.10 Reset and Power Down Control
Register ........................................ 44
6.2.11 USB PLL Parameter Register .... 46
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 3
November 2011 • 3
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