AR0141CS(2015) Ver la hoja de datos (PDF) - ON Semiconductor

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Fabricante

AR0141CS
(Rev.:2015)

1/4-Inch Digital Image Sensor

ON Semiconductor 

AR0141CS: 1/4-Inch Digital Image Sensor

General Description

Figure 3:

Typical Configuration: Parallel Pixel Data Interface

Digital Digital

I/O core

power1 power1

PLL Analog Analog

power1 power1 power1

VDD_IO VDD

VDD_PLL VAA VAA_PIX

Master clock

(6-50 MHz)

From

Controller

EXTCLK

SADDR

SDATA

SCLK

TRIGGER

OE_BAR

RESET_BAR

TEST

DGND

VDD_IO

VDD

VDD_PLL

VAA

VAA_PIX

Digital

ground

DOUT [11:0]

PIXCLK

LINE_VALID

FRAME_VALID

FLASH

SHUTTER

AGND

To

controller

Analog

ground

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-

face is used.

4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply

are mounted as close as possible to the pad. Actual values and results may vary depending on lay-

out and design considerations. Check the AR0141CS demo headboard schematics for circuit recom-

mendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

7. The EXTCLK input is limited to 6-50 MHz.

AR0141CS DS Rev. D Pub. 6/15 EN

8

©Semiconductor Components Industries, LLC, 2015.

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