1EDI30J12CP Ver la hoja de datos (PDF) - Infineon Technologies
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1EDI30J12CP Datasheet PDF : 28 Pages
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EiceDRIVER™ Enhanced
1EDI30J12CP
Pin Configuration and Description
1
Pin Configuration and Description
The pin configuration for 1EDI30J12CP in a PG-DSO-19-4 wide body package is shown in Figure 1 and Table 1.
N.C.
1
20
BSEN
2
19
CLJFG
3
18
VREG
4
17
N.C.
5
VEE2
6
15
MDrv
7
14
JFDrv
8
13
VCC2
9
12
N.C.
10
11
Figure 1
PG-DSO-19-4 (300mil)
Pin Configuration PG-DSO-19-4
N.C.
VCC1
IN
GND1
EN
N.C.
N.C.
N.C.
N.C.
Table 1 Pin Configuration 1EDI30J12CP in PG-DSO-19-4, Wide Body
Pin Symbol Description
1 N.C.
Internally not connected1)
2 BSEN Bootstrap Enable
For bootstrap operation connect this pin to VCC2, for non bootstrap operation to VREG
3 CLJFG Reserved2)
4 VREG Voltage Regulator Output
VREG is the output of the integrated linear regulator and the negative power supply for the gate
drivers
5 N.C.
Internally not connected1)
6 VEE2
Negative Power Supply Output Side
VEE2 is the input of the integrated linear regulator
7 MDrv
MOSFET Driver Output
8 JFDrv JFET Driver Output
9 VCC2
10 N.C.
11 N.C.
12 N.C.
13 N.C.
14 N.C.
Positive Power Supply Output Side
VCC2 is the positive supply input of the JFET driver and MOSFET driver, connected to the
sources of the JFET and the MOSFET
Internally not connected1)
Internally not connected1)
Internally not connected1)
Internally not connected1)
Internally not connected1)
Preliminary Datasheet
4
Rev. 1.3, 2014-11-12
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