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MT6260A

GSM/GPRS/EDGE-RX SOC Processor Technical Brief

MediaTek Inc 

MT6260A

GSM/GPRS/EDGE-RX SOC Processor Technical Brief

v1.1 Confidential A

Preface

Acronyms for register types

R/W

RO

RC

WO

W1S

W1C

For both read and write access

Read only

Read o ly. After the register bank is read, every bit that is HIGH(1) will be cleared to LOW(0)

aut matic lly.

Write only

Write o y. When data bits are written to the register bank, every bit that is HIGH(1) will

cause the corresponding bit to be set to 1. Data bits that are LOW(0) have no effects on the

corresponding bit

Write only. When data bits are written to the register bank, every bit that is HIGH(1) will

cause the corresponding bit to be cleared to 0. Data bits that are LOW(0) have no effects on

the corresponding it.

MediaTek Confidential

© 2013 MediaTek Inc.

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this informa ion in whole or in part is strictly prohibited.

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