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ML4824IX Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza
componentes Descripción
Fabricante
ML4824IX
Fairchild
Fairchild Semiconductor Fairchild
ML4824IX Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ML4824
PIN CONFIGURATION
ML4824
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
IEAO 1
16 VEAO
IAC 2
ISENSE 3
VRMS 4
SS 5
15 VFB
14 VREF
13 VCC
12 PFC OUT
VDC 6
RAMP 1 7
11 PWM OUT
10 GND
RAMP 2 8
9 DC ILIMIT
TOP VIEW
PIN DESCRIPTION
PIN NAME
1 IEAO
2 IAC
3 ISENSE
4 VRMS
5 SS
6 VDC
7 RAMP 1
8 RAMP 2
FUNCTION
PFC transconductance current error
amplifier output
PFC gain control reference input
Current sense input to the PFC current
limit comparator
Input for PFC RMS line voltage
compensation
Connection point for the PWM soft start
capacitor
PWM voltage feedback input
Oscillator timing node; timing set
by RTCT
When in current mode, this pin
functions as as the current sense input;
when in voltage mode, it is the PWM
input from PFC output (feed forward
ramp).
PIN NAME
9 DC ILIMIT
10 GND
FUNCTION
PWM current limit comparator input
Ground
11 PWM OUT PWM driver output
12 PFC OUT PFC driver output
13 VCC
Positive supply (connected to an
internal shunt regulator)
14 VREF
Buffered output for the internal 7.5V
reference
15 VFB
PFC transconductance voltage error
amplifier input
16 VEAO
PFC transconductance voltage error
amplifier output
2
REV. 1.01 12/7/2000

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