RTL8192SE Ver la hoja de datos (PDF) - Realtek Semiconductor

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componentes Descripción

Fabricante

RTL8192SE

SINGLE-CHIP IEEE 802.11b/g/n 2T2R WLAN CONTROLLER w/PCI EXPRESS INTERFACE

Realtek Semiconductor 

5. Pin Descriptions

The following signal type codes are used in the tables:

I: Input

O: Output

T/S: Tri-State bi-directional input/output pin

S/T/S: Sustained Tri-State

O/D: Open Drain

P: Power pin

RTL8192SE

Datasheet

5.1. PCI Express Transceiver Interface

Symbol

HSIN/HSIP

HSON/HSOP

REFCLK_P/REFCLK_N

CLKREQn

WAKEn

PERSTn

Table 1. PCI Express Transceiver Interface

Type Pin No Description

I

48/49 PCI Express Receive Differential Pair

O

44/45 PCI Express Transmit Differential Pair

I

46/47 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm

O

36 Reference Clock Request Signal.

This signal is used by the RTL8192SE-GR to request starting of the PCI

Express reference clock

O/D

35 Power Management Event: Open drain, active low.

Used to reactivate the PCI Express slot’s main power rails and reference

clocks.

I

37 PCI Express Reset Signal: Active low.

When the PERSTB is asserted at power-on state, the RTL8192SE-GR

returns.

to a pre-defined reset state and is ready for initialization and configuration

after the de-assertion of the PERSTB.

5.2. EEPROM Interface

Symbol

EESK

EEDI

EEDO

EECS

Type

O

O

IO

O

Table 2. EEPROM Interface

Pin No Description

66 EESK in 93C46 Programming or Auto-Load Mode

65 EEDI in 93C46 Programming or Auto-Load Mode

64 EEDO in 93C46 Programming or Auto-Load Mode

67 EEPROM Chip Select

93C46 chip select.

Single-Chip IEEE 802.11b/g/n 2T2R WLAN Controller 7

with PCI Express Interface

Track ID: JATR-1076-21 Rev. 1.1

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