MC74HC4020A_14 Ver la hoja de datos (PDF) - ON Semiconductor
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MC74HC4020A_14 Datasheet PDF : 8 Pages
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MC74HC4020A
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V −55 to 25°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 5)
2.0
10
3.0
15
4.5
30
6.0
50
9.0
8.0 MHz
14
12
28
25
50
40
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q1*
(Figures 4 and 5)
2.0
96
3.0
63
4.5
31
6.0
25
106
115
ns
71
88
36
40
30
35
tPHL Maximum Propagation Delay, Reset to Any Q
(Figures 3 and 5)
2.0
65
3.0
30
4.5
30
6.0
26
72
90
ns
36
40
35
40
32
35
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 4 and 5)
2.0
69
3.0
40
4.5
17
6.0
14
80
90
ns
45
50
21
28
15
22
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 5)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
15
19
Cin Maximum Input Capacitance
10
10
10
pF
* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n−1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n−1)] ns
CPD Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
38
pF
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
trec Minimum Recovery Time, Reset Inactive to Clock
(Figure 3)
tw
Minimum Pulse Width, Clock
(Figure 2)
tw
Minimum Pulse Width, Reset
(Figure 3)
tr, tf Maximum Input Rise and Fall Times
(Figure 2)
Guaranteed Limit
VCC
V −55 to 25°C ≤85°C ≤125°C Unit
2.0
30
3.0
20
4.5
5
6.0
4
40
50
ns
25
30
8
12
6
9
2.0
70
3.0
40
4.5
15
6.0
13
80
90
ns
45
50
19
24
16
20
2.0
70
3.0
40
4.5
15
6.0
13
80
90
ns
45
50
19
24
16
20
2.0
1000
1000 1000 ns
3.0
800
800
800
4.5
500
500
500
6.0
400
400
400
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