MAX11606_09 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX11606_09

2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

Maxim Integrated 

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

TIMING CHARACTERISTICS (Figure 1) (continued)

(VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V

(MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless other-

wise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Rise Time of SCL Signal

(Current Source Enabled)

tRCL Measured from 0.3VDD to 0.7VDD

20

80

ns

Rise Time of SCL Signal after

Acknowledge Bit

tRCL1 Measured from 0.3VDD to 0.7VDD

20

160

ns

Fall Time of SCL Signal

tFCL Measured from 0.3VDD to 0.7VDD

20

Rise Time of SDA Signal

tRDA Measured from 0.3VDD to 0.7VDD

20

Fall Time of SDA Signal

tFDA Measured from 0.3VDD to 0.7VDD (Note 11)

20

Setup Time for STOP (P) Condition tSU,STO

160

Capacitive Load for Each Bus Line CB

Pulse Width of Spike Suppressed

tSP

(Notes 10 and 13)

0

80

ns

160

ns

160

ns

ns

400

pF

10

ns

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at VDD = 5V and the MAX11607/MAX11609/MAX11611

are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs.

Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Offset nulled.

Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion

time does not include acquisition time. SCL is the conversion clock in the external clock mode.

A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.

The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.

When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a

0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).

ADC performance is limited by the converter’s noise floor, typically 300µVP-P.

Note 9: Measured as follows for the MAX11607/MAX11609/MAX11611:

[ ] ⎡

⎢

⎣

VFS(3.6V) − VFS(2.7V)

×

2N −1⎤

VREF

⎥

⎦

(3.6V − 2.7V)

and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:

[ ] ⎡

⎢

⎣

VFS(5.5V) − VFS(4.5V)

×

2N −1⎤

VREF

⎥

⎦

(5.5V − 4.5V)

Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s

falling edge (see Figure 1).

Note 11: The minimum value is specified at TA = +25°C.

Note 12: CB = total capacitance of one bus line in pF.

Note 13: fSCL must meet the minimum clock low time plus the rise/fall times.

_______________________________________________________________________________________ 5

Share Link: