HEF4015B Ver la hoja de datos (PDF) - NXP Semiconductors.
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HEF4015B Datasheet PDF : 15 Pages
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NXP Semiconductors
HEF4015B
Dual 4-bit static shift register
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 1500 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 6300 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 17000 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
12. Waveforms
VI
nCP input
VSS
VOH
nQn output
VOL
VM
tPHL
90 %
VM
10 %
tt
tPLH
tt
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Measurement points are given in Table 9.
Fig 4. Waveforms showing nCP propagation delays and nQn transition times
VI
nCP input
VSS
VI
nD input
VSS
tW
VM
VM
VM
1/fmax
th
th
VM
VM
VM
VM
tsu
tsu
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Fig 5.
The shaded area indicates where the input is permitted to change for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Waveforms showing set-up times, hold times, and minimum clock pulse width
HEF4015B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
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