MK2771-15 Ver la hoja de datos (PDF) - Integrated Device Technology
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MK2771-15 Datasheet PDF : 7 Pages
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MK2771-15
VCXO AND SET-TOP CLOCK SOURCE
VCXO AND SYNTHESIZER
Pin Descriptions
Pin
Number
1
2
3
4, 5, 8
6
7
9
10, 18,
19, 24
11
12
13
14
15
16
17
20
21, 22
23
25
26
27
28
Pin
Name
PCS0
X2
X1
VDD
VIN
VDDIO
SC
GND
Pin Type
Pin Description
Input
XO
XI
Power
Input
Power
Tri-level input
Power
Processor clock select 0. Selects PCLKs on pins 11 and 12. See
table above. Internal pull-up resistor.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to +5 V.
Voltage input to VCXO. Zero to 3 V signal which controls the
frequency of the VCXO.
Connect to +3.3 V or +5 V. Amplitude of inputs must, and outputs
will, match this.
Communications clock select pin. Biased to M level if floating
Connect to ground.
PCLK1
PCLK2
PCS1
ACLK
DC
13.5M
CCLK2
PCS2
VDD
CCLK1
27M
54M
ACS0
ACS1
Output
Output
Input
Output
—
Output
Output
Input
Power
Output
Output
Output
Input
Input
Processor clock output number 1. Determined by status of
PCS2:0.
Processor clock output number 2. Determined by status of
PCS2:0.
Processor clock select 1. Selects PCLKs on pins 11 and 12. See
table above. Internal pull-up resistor.
Audio clock output. Determined by status of ACS1, ACS0 per
table above.
Don’t Connect anything to this pin.
13.50 MHz VCXO clock output.
Communications clock output 2 determined by status of SC per
table above.
Processor clock select 2. Selects PCLKs on pins 11 and 12. See
table above. Internal pull-up resistor.
Connect to +5 V.
Communications clock output 1 determined by status of SC per
table above.
27.00 MHz VCXO clock output.
54.00 MHz VCXO clock output.
Audio clock select 0. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
Audio clock select 1. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
IDT™ VCXO AND SET-TOP CLOCK SOURCE
3
MK2771-15 REV G 122109
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