RD28F1602C3B110_03 Ver la hoja de datos (PDF) - Intel

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RD28F1602C3B110_03

3 Volt Intel® Advanced+ Boot Block Flash Memory(C3) Stacked-Chip Scale Package Family

Intel 

Contents

5.4 DC Characteristics.............................................................................................................. 26

5.5 Flash AC Characteristics. ................................................................................................... 29

5.6 Flash AC Characteristics—Write Operations...................................................................... 31

5.7 Flash Erase and Program Timings(1)................................................................................. 31

5.8 Flash Reset Operations ...................................................................................................... 34

5.9 SRAM AC Characteristics—Read Operations.................................................................... 35

5.10 SRAM AC Characteristics—Write Operations .................................................................... 37

5.11 SRAM Data Retention Characteristics—Extended Temperature ....................................... 39

6.0 Migration Guide Information ...................................................................................................... 40

7.0 System Design Considerations.................................................................................................. 41

7.1 Background......................................................................................................................... 41

7.1.1 Flash + SRAM Footprint Integration ...................................................................... 41

7.1.2 Advanced+ Boot Block Flash Memory Features ................................................... 41

7.2 Flash Control Considerations ............................................................................................. 41

7.2.1 F-RP# Connected to System Reset....................................................................... 42

7.2.2 F-VCC, F-VPP and F-RP# Transition .................................................................... 42

7.3 Noise Reduction ................................................................................................................. 43

7.4 Simultaneous Operation ..................................................................................................... 44

7.4.1 SRAM Operation during Flash “Busy” ................................................................... 45

7.4.2 Simultaneous Bus Operations ............................................................................... 45

7.5 Printed Circuit Board Notes ................................................................................................ 45

7.6 System Design Notes Summary......................................................................................... 45

Appendix A Program/Erase Flowcharts ............................................................................................. 46

Appendix B CFI Query Structure ........................................................................................................ 52

Appendix C Word-Wide Memory Map Diagrams ............................................................................... 59

Appendix D Device ID Table ................................................................................................................ 62

Appendix E Protection Register Addressing..................................................................................... 63

Appendix F Mechanical and Shipping Media Details........................................................................ 64

Appendix G Additional Information .................................................................................................... 68

Appendix H Ordering Information....................................................................................................... 69

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