7C4261V-25 Ver la hoja de datos (PDF) - Cypress Semiconductor
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7C4261V-25 Datasheet PDF : 16 Pages
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CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
Table 2. Status Flags
Number of Words in FIFO
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
FF PAF PAE EF
0
1 to n[2]
0
1 to n[2]
0
1 to n[2]
0
1 to n[2]
HH
HH
LL
LH
(n + 1) to (1638 − (m + 1)) (n + 1) to (32768 − (m + 1)) (n + 1) to (65536 − (m + 1)) (n + 1) to (131072 −
HH
(m + 1))
(16384 − m)[3] to 16383 (32768 − m)[3] to 32767 (65536 − m)[3] to 65535 (131072 − m)[3] to 131071 H L
HH
HH
16384
32768
65536
131072
L L HH
Width-Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C42x1Vs. Any
word width can be attained by adding additional CY7C42x1Vs.
When the CY7C42x1V is in a Width-Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
The CY7C4261/71/81/91V devices provide five flag pins to
indicate the condition of the FIFO contents. Empty, Full, PAE,
and PAF are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK,
i.e., it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
RESET (RS)
DATA IN (D) 18 9
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V
FF
EF
FULL FLAG (FF) # 2
9
RESET (RS)
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
CY7C4261V
PROGRAMMABLE(PAE)
CY7C4271V EMPTY FLAG (EF) #1
CY7C4281V
CY7C4291V EMPTY FLAG (EF) #2
FF
EF
9 DATA OUT (Q) 18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 16k/32k/64k/128k x 9 Low-Voltage Deep Sync FIFO Memory
Used in a Width-Expansion Configuration
Notes:
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06013 Rev. *B
Page 5 of 16
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