7C4281V-25(2003) Ver la hoja de datos (PDF) - Cypress Semiconductor
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7C4281V-25 Datasheet PDF : 16 Pages
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CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
16k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
5
0
(MSB)
Default Value = 000h
87
0
Full Offset (LSB) Reg
Default Value = 007h
8
5
0
(MSB)
Default Value = 000h
64k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
32k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
86
0
(MSB)
Default Value = 000h
87
0
Full Offset (LSB) Reg
Default Value = 007h
86
0
(MSB)
Default Value = 000h
128k x 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the read
and write pointers.
Table 1. Writing the Offset Registers[1]
LD WEN WCLK
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
87
0
(MSB)
Default Value = 000h
8
0
(MSB)
Default Value = 000h
1
0
Write Into FIFO
87
0
Full Offset (LSB) Reg
Default Value = 007h
87
0
Full Offset (LSB) Reg
Default Value = 007h
1
1
No Operation
87
0
(MSB)
Default Value = 000h
8
0
(MSB)
Default Value = 000h
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
Figure 1. Offset Register Location and Default Values
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
It is not necessary to write to all the offset registers at one time. RCLK when the FIFO contains (n+1) or greater unread words.
A subset of the offset registers can be written; then by bringing The number formed by the full offset least significant bit
the WEN2/LD input HIGH, the FIFO is returned to normal read register and full offset most significant bit register is referred to
and write operation. The next time WEN2/LD is brought LOW, as m and determines the operation of PAF. PAE is synchronized to
a write operation stores data in the next offset register in the LOW-to-HIGH transition of WCLK by one flip-flop and is
sequence.
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261V (16k – m), CY7C4271V
(32k – m), CY7C4281V (64k - m) and CY7C4291V (128k – m).
PAF is set HIGH by the LOW-to-HIGH transition of WCLK
when the number of available memory locations is greater
than m.
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06013 Rev. *A
Page 4 of 16
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