73K321L Ver la hoja de datos (PDF) - TDK Corporation

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Fabricante

73K321L

CCITT V.23, V.21 Single-Chip Modem

TDK Corporation 

73K321L

CCITT V.23, V.21

Single-Chip

PARALLEL MICROPROCESSOR CONTROL INTERFACE (continued)

NAME

WR

PLCC/DIP

PIN NUMBER

13

TYPE DESCRIPTION

I

Write. A low on this informs the 73K321L that data is available on

AD0-AD7 for writing into an internal register. Data is latched on the

rising edge of WR. No data is written unless both WR and the latched

CS are low.

SERIAL MICROPROCESSOR CONTROL INTERFACE

AD0-AD2

4-6

I

Register Address Selection. These lines carry register addresses and

should be valid during any read or write operation.

DATA (AD7)

11

I/O Serial Control Data. Data for a read/write operation is clocked in or

out on the falling edge of the EXCLK pin. The direction of data flow is

controlled by the RD pin. RD low outputs data. RD high inputs data.

RD

14

I

Read. A low on this input informs the 73K321L that data or status

information is being read by the processor. The falling edge of the

RD signal will initiate a read from the addressed register. The RD

signal must continue for eight falling edges of EXCLK in order to read

all eight bits of the referenced register. Read data is provided LSB

first. Data will not be output unless the RD signal is active.

WR

13

I

Write. A low on this input informs the 73K321L that data or status

information has been shifted in through the DATA pin and is available

for writing to an internal register. The normal procedure for a write is

to shift in data LSB first on the DATA pin for eight consecutive falling

edges of EXCLK and then to pulse WR low. Data is written on the

rising edge of WR.

NOTE: The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the address only. See the Serial Control Timing diagrams on

page 18

4

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