AT24C128-10PI-1.8 Ver la hoja de datos (PDF) - Atmel Corporation

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AT24C128-10PI-1.8

Two-wire Serial EEPROMs

Atmel Corporation 

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

AT24C128/256

Device

Addressing

0670S–SEEPR–5/06

The 128K/256K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Figure 7 on page 11). The device address

word consists of a mandatory one, zero sequence for the first five most significant bits as

shown. This is common to all two-wire EEPROM devices.

The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on

the same bus. These bits must compare to their corresponding hardwired input pins. The A1

and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the

pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is

initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the device will return to a standby state.

DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows the

user to write protect the whole memory when the WP pin is at VCC.

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