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DP80390

Pipelined High Performance 8-bit Microcontroller

Digital Core Design 

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

♦ VHDL & VERILOG test bench environment

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor and

major versions changes

● Delivery the documentation updates

● Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows using IP Core in

single FPGA bitstream and ASIC implementa-

tion. It also permits FPGA prototyping before

ASIC production.

Unlimited Designs license allows using IP Core

in unlimited number of FPGA bitstreams and

ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

● Single Design license for

○ VHDL, Verilog source code called HDL Sour-

ce

○ Encrypted, or plain text EDIF called Netlist

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ Netlist to HDL Source

○ Single Design to Unlimited Designs

DESIGN FEATURES

♦ PROGRAM MEMORY:

The DP80390 soft core is dedicated for

operation with Internal and External Pro-

gram Memory. It maximal linear size is

equal to 8 MB. Internal Program Memory

can be implemented as:

○ ROM located in address range between

0000h ÷ (ROMsize-1)

○ RAM located in address range between

(64kB-RAMsize) ÷ FFFFh

External Program Memory can be im-

plemented as ROM or RAM located in ad-

dress range between ROMsize ÷ 8 MB ex-

cluding area occupied by RAMsize.

♦ INTERNAL DATA MEMORY:

The DP80390 can address Internal Data

Memory of up to 256 bytes The Internal

Data Memory can be implemented as Sin-

gle-Port synchronous RAM.

♦ EXTERNAL DATA MEMORY:

The DP80390 soft core can address up

to 16 MB of External Data Memory. Extra

DPX (Data Pointer eXtended) register is

used for segments swapping.

♦ USER SPECIAL FUNCTION REGISTERS:

Up to 104 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP80390 design. ESFRs are memory

mapped into Direct Memory between ad-

dresses 0x80 and 0xFF in the same man-

ner as core SFRs and may occupy any ad-

dress that is not occupied by a core SFR.

♦ WAIT STATES SUPPORT:

The DP80390 soft core is dedicated for

operation with wide range of Program and

Data memories. Slow Program and Exter-

nal Data memory may assert a memory

Wait signal to hold up CPU activity.

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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