DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor and
major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
All trademarks mentioned in this document
are trademarks of their respective owners.
DESIGN FEATURES
♦ PROGRAM MEMORY:
The DP8051 soft core is dedicated for
operation with Internal and External Pro-
gram Memory. Internal Program Memory
can be implemented as:
○ ROM located in address range between
0000h ÷ (ROMsize-1)
○ RAM located in address range between
(RAMsize-1) ÷ FFFFh
External Program Memory can be im-
plemented as ROM or RAM located in ad-
dress range between ROMsize ÷ RAMsize.
♦ INTERNAL DATA MEMORY:
The DP8051 can address Internal Data
Memory of up to 256 bytes The Internal
Data Memory can be implemented as Sin-
gle-Port synchronous RAM.
♦ EXTERNAL DATA MEMORY:
The DP8051 soft core can address up to
16 MB of External Data Memory. Extra
DPX (Data Pointer eXtended) register is
used for segments swapping.
♦ USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Func-
tion Registers (ESFRs) may be added to
the DP8051 design. ESFRs are memory
mapped into Direct Memory between ad-
dresses 80 hex and FF hex in the same
manner as core SFRs and may occupy any
address that is not occupied by a core
SFR.
♦ WAIT STATES SUPPORT:
The DP8051 soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and Exter-
nal Data memory may assert a memory
Wait signal to hold up CPU activity.
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