5.1.3 PCICMDâPCI Command ...........................................................86
5.1.4 PCISTSâPCI Status .................................................................87
5.1.5 RIDâRevision Identification ......................................................88
5.1.6 CCâClass Code.......................................................................88
5.1.7 MLTâMaster Latency Timer ......................................................89
5.1.8 HDRâHeader Type ..................................................................89
5.1.9 SVIDâSubsystem Vendor Identification......................................89
5.1.10 SIDâSubsystem Identification ..................................................90
5.1.11 CAPPTRâCapabilities Pointer ....................................................90
5.1.12 PXPEPBARâPCI Express* Egress Port Base Address (IntelÂź
82Q965/82G965/82P965 (G)MCH Only)......................................91
5.1.13 MCHBARâ(G)MCH Memory-Mapped Register Range Base..............92
5.1.14 GGCâGMCH Graphics Control Register (IntelÂź 82Q965, 82Q963,
82G965 GMCH Only)................................................................93
5.1.15 DEVENâDevice Enable.............................................................94
5.1.16 PCI EXPRESS*XBARâPCI Express* Register Range Base Address
(IntelÂź 82Q965, 82G965, 82P965 (G)MCH Only) ..........................95
5.1.17 DMIBARâRoot Complex Register Range Base Address ..................97
5.1.18 PAM0âProgrammable Attribute Map 0........................................98
5.1.19 PAM1âProgrammable Attribute Map 1........................................99
5.1.20 PAM2âProgrammable Attribute Map 2...................................... 100
5.1.21 PAM3âProgrammable Attribute Map 3...................................... 101
5.1.22 PAM4âProgrammable Attribute Map 4...................................... 102
5.1.23 PAM5âProgrammable Attribute Map 5...................................... 103
5.1.24 PAM6âProgrammable Attribute Map 6...................................... 104
5.1.25 LACâLegacy Access Control.................................................... 105
5.1.26 REMAPBASEâRemap Base Address Register.............................. 107
5.1.27 REMAPLIMITâRemap Limit Address Register ............................. 107
5.1.28 SMRAMâSystem Management RAM Control .............................. 108
5.1.29 ESMRAMCâExtended System Management RAM Control ............. 109
5.1.30 TOMâTop of Memory............................................................. 110
5.1.31 TOUUDâTop of Upper Usable DRAM......................................... 111
5.1.32 GBSMâGraphics Base of Stolen Memory (IntelÂź 82G965, 82Q965,
82063Q GMCH Only).............................................................. 111
5.1.33 TSEGMBâTSEG Memory Base ................................................. 112
5.1.34 TOLUDâTop of Low Usable DRAM ............................................ 113
5.1.35 ERRSTSâError Status ............................................................ 114
5.1.36 ERRCMDâError Command ...................................................... 115
5.1.37 SMICMDâSMI Command........................................................ 116
5.1.38 SKPDâScratchpad Data ......................................................... 117
5.1.39 CAPID0âCapability Identifier .................................................. 117
5.2 MCHBAR Registers.............................................................................. 118
5.2.1 CHDECMISCâChannel Decode Miscellaneous............................. 121
5.2.2 C0DRB0âChannel 0 DRAM Rank Boundary Address 0 ................. 122
5.2.3 C0DRB1âChannel 0 DRAM Rank Boundary Address 1 ................. 123
5.2.4 C0DRB2âChannel 0 DRAM Rank Boundary Address 2 ................. 124
5.2.5 C0DRB3âChannel 0 DRAM Rank Boundary Address 3 ................. 124
5.2.6 C0DRA01âChannel 0 DRAM Rank 0,1 Attribute ......................... 125
5.2.7 C0DRA23âChannel 0 DRAM Rank 2,3 Attribute ......................... 126
5.2.8 C0CYCTRKPCHGâChannel 0 CYCTRK Precharge......................... 126
5.2.9 C0CYCTRKACTâChannel 0 CYCTRK ACT ................................... 127
5.2.10 C0CYCTRKWRâChannel 0 CYCTRK WR ..................................... 128
5.2.11 C0CYCTRKRDâChannel 0 CYCTRK READ................................... 128
5.2.12 C0CYCTRKREFRâChannel 0 CYCTRK REFR ................................ 129
5.2.13 C0CKECTRLâChannel 0 CKE Control ........................................ 130
Datasheet
5