9.2.3 STSâDevice Status ............................................................... 290
9.2.4 RIDâRevision ID................................................................... 291
9.2.5 CCâClass Code..................................................................... 291
9.2.6 CLSâCache Line Size............................................................. 291
9.2.7 MLTâMaster Latency Timer .................................................... 292
9.2.8 HTYPEâHeader Type ............................................................. 292
9.2.9 BISTâBuilt In Self Test .......................................................... 292
9.2.10 HECI_MBARâHECI MMIO Base Address .................................... 293
9.2.11 SSâSub System Identifiers .................................................... 293
9.2.12 CAPâCapabilities Pointer........................................................ 294
9.2.13 INTRâInterrupt Information ................................................... 294
9.2.14 MGNTâMinimum Grant .......................................................... 294
9.2.15 MLATâMaximum Latency ....................................................... 295
9.2.16 HFSâHost Firmware Status .................................................... 295
9.2.17 PIDâPCI Power Management Capability ID ............................... 295
9.2.18 PCâPCI Power Management Capabilities................................... 296
9.2.19 PMCSâPCI Power Management Control and Status .................... 297
9.2.20 MIDâMessage Signaled Interrupt Identifiers ............................. 299
9.2.21 MCâMessage Signaled Interrupt Message Control ...................... 299
9.2.22 MAâMessage Signaled Interrupt Message Address ..................... 300
9.2.23 MUAâMessage Signaled Interrupt Upper Address (Optional)........ 300
9.2.24 MDâMessage Signaled Interrupt Message Data ......................... 300
9.2.25 HIDMâHECI Interrupt Delivery Mode ....................................... 301
9.3 PT IDER Configuration Register Details (Device 3, Function 2) (IntelÂź 82Q965
GMCH Only) ...................................................................................... 302
9.3.1 IDâIdentification .................................................................. 303
9.3.2 CMDâCommand Register ....................................................... 303
9.3.3 STSâDevice Status ............................................................... 304
9.3.4 RIDâRevision ID................................................................... 305
9.3.5 CCâClass Codes ................................................................... 306
9.3.6 CLSâCache Line Size............................................................. 306
9.3.7 MLTâMaster Latency Timer .................................................... 306
9.3.8 HTYPEâHeader Type ............................................................. 307
9.3.9 PCMDBAâPrimary Command Block IO Bar ................................ 307
9.3.10 PCTLBAâPrimary Control Block Base Address............................ 308
9.3.11 SCMDBAâSecondary Command Block Base Address................... 308
9.3.12 SCTLBAâSecondary Control Block base Address ........................ 309
9.3.13 LBARâLegacy Bus Master Base Address ................................... 309
9.3.14 SSâSub System Identifiers .................................................... 310
9.3.15 EROMâExpansion ROM Base Address....................................... 310
9.3.16 CAPâCapabilities Pointer........................................................ 311
9.3.17 INTRâInterrupt Information ................................................... 311
9.3.18 MGNTâMinimum Grant .......................................................... 312
9.3.19 MLATâMaximum Latency ....................................................... 312
9.3.20 PIDâPCI Power Management Capability ID ............................... 312
9.3.21 PCâPCI Power Management Capabilities................................... 313
9.3.22 PMCSâPCI Power Management Control and Status .................... 314
9.3.23 MIDâMessage Signaled Interrupt Capability ID ......................... 315
9.3.24 MCâMessage Signaled Interrupt Message Control ...................... 316
9.3.25 MAâMessage Signaled Interrupt Message Address ..................... 316
9.3.26 MAUâMessage Signaled Interrupt Message Upper Address .......... 317
9.3.27 MDâMessage Signaled Interrupt Message Data ......................... 317
9.4 (KT) Redirection Configuration Register Details (Device 3, Function 3) (IntelÂź
82Q965 GMCH Only)........................................................................... 318
9.4.1 IDâIdentification .................................................................. 319
10
Datasheet