100310 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
100310 Datasheet PDF : 6 Pages
| |||
Industrial Version
DC Electrical Characteristics (Note 8)
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −40°C
Min
Max
TC = 0°C to +85°C
Min
Max
Units
Conditions
VOH
VOL
VOHC
VOLC
VBB
VDIFF
VCM
VIH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Reference Voltage
Input Voltage Differential
Common Mode Voltage
Input HIGH Voltage
−1085
−870
−1025
−870
−1830 −1575 −1830 −1620
−1095
−1035
−1565
−1610
−1395 −1255 −1380 −1260
150
150
VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5
−1170
−870
−1165
−870
mV VIN = VIH (Max) Loading with
mV or VIL (Min)
50Ω to −2.0V
mV VIN = VIH
Loading with
mV or VIL (Min)
50Ω to −2.0V
mV IVBB = −250 µA
mV Required for Full Output Swing
V
mV Guaranteed HIGH Signal for
All Inputs
VIL
Input LOW Voltage
−1830 −1480 −1830 −1475
mV Guaranteed LOW Signal for
All Inputs
IIL
Input LOW Current
0.50
0.50
µA VIN = VIL (Min)
IIH
Input HIGH Current
240
240
µA VIN = VIH (Max)
ICBO
Input Leakage Current
−10
−10
µA
VIN = VEE
IEE
Power Supply Current
−100
−40
−100
−40
mA Inputs Open
Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = −40°C
Min Typ Max
TC = +25°C
Min Typ Max
TC = +85°C
Units
Min Typ Max
Conditions
fMAX
tPLH
tPHL
Max Toggle Frequency
CLKIN A/B to Qn 750
SEL to Qn 575
Propagation Delay,
CLKINn, to CLKn
Differential 0.78
0.88
0.98
750
575
0.82
0.92
1.02
750
575
0.89
1.01
1.09
MHz
MHz
ns Figure 3
Single-Ended 0.78 0.95 1.18 0.82 0.98 1.22 0.89 1.06 1.29
tPLH
Propagation Delay
tPHL
SEL to Output
0.70 0.99 1.20 0.80 1.02 1.25 0.85 1.10 1.35 ns Figure 2
tPS
LH-HL Skew
10 30
10 30
10 30
(Note 9)(Note 12)
tOSLH
Gate-Gate Skew LH
20 50
20 50
20
50
ps (Note 10)(Note 12)
tOSHL
Gate-Gate Skew HL
20 50
20 50
20 50
(Note 10)(Note 12)
tOST
Gate-Gate LH-HL Skew
30 60
30 60
30 60
(Note 11)(Note 12)
tS
Setup Time
300
300
300
ps
SEL to CLKINn
tH
Setup Time
0
0
0
ps
SEL to CLKINn
tTLH
Transition Time
275 510 750 275 500 750 275 480 750 ps Figure 4
tTHL
20% to 80%, 80% to 20%
Note 9: tPS describes opposite edge skews, i.e. the difference between the delay of a differential output signal pair's LOW-to-HIGH and HIGH-to-LOW prop-
agation delays. With differential signal pairs, a LOW-to-HIGH or HIGH-to-LOW transition is defined as the transition of the true output or input pin.
Note 10: tOSLH describes in-phase gate-to-gate differential propagation skews with all differential outputs going LOW-to-HIGH; tOSHL describes the same
conditions except with the outputs going HIGH-to-LOW.
Note 11: tOST describes the maximum worst case difference in any of the tPS, tOSLH or tOST delay paths combined.
Note 12: The skew specifications pertain to differential I/O paths.
www.fairchildsemi.com
4
Share Link: 