GS9091B Ver la hoja de datos (PDF) - Semtech Corporation
Número de pieza
componentes Descripción
Fabricante
GS9091B Datasheet PDF : 73 Pages
| |||
Table 1-1: Ball List and Description (Continued)
Ball
Name
Timing
Type
K3
IOPROC_EN
Non
Synchronous
Input
K4
RESET
Non
Synchronous
Input
K5
SCLK_TCK
Non
Synchronous
Input
K6
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
Description
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device
are enabled:
• Illegal Code Remapping
• EDH CRC Error Correction
• Ancillary Data Checksum Error Correction
• TRS Error Correction
• EDH Flag Detection
To enable a subset of these features, keep IOPROC_EN HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for Video mode or
Ancillary Data Extraction mode, IOPROC_EN must be set HIGH (see
Section 3.10).
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting
or to reset the JTAG test sequence.
Host Mode (JTAG_EN = LOW):
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high
impedance.
When set HIGH, normal operation of the device resumes 10usec
after the LOW-to-HIGH transition of the RESET signal.
JTAG Test Mode (JTAG_EN = HIGH):
When asserted LOW, all functional blocks will be set to default and
the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Clock / Test Clock. All JTAG / Host Interface address and
data are shifted into/out of the device synchronously with this
clock.
Host Mode (JTAG_EN = LOW):
SCLK_TCK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG_EN = HIGH):
SCLK_TCK operates as the JTAG test clock, TCK.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Input / Test Data Input
Host Mode (JTAG_EN = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG_EN = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
10 of 73
Proprietary & Confidential
Share Link: 