LA6324N_12 Ver la hoja de datos (PDF) - SANYO -> Panasonic
Número de pieza
componentes Descripción
Fabricante
LA6324N_12 Datasheet PDF : 5 Pages
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LA6324N,6324NM
Test Circuit
1. Input offset voltage VIO
R1
R1
R2
VCC R2
-
VCC
+
+
NULL
-
VF1
+1.4V
VEE C
VIO
=
VF1
1+R2/R1
2. Input offset current IIO
R1 R
VCC R2
-
VCC
R1
R+
R2
+1.4V
+
NULL
-
VEE
VF2
C
IIO =
VF2 - VF1
R(1+R2/R1)
3. Input bias current IB
R1 R
VCC R2
-
VCC
R1
+
+
NULL
-
VF3
R2
+1.4V
VEE C
IB =
VF4 - VF3
2R(1+R2/R1)
R1
VCC R2
-
VCC
R1
R+
R2
+1.4V
+
NULL
-
VEE
VF4
C
4. Common-mode rejection ratio CMR
Common-mode input voltage range VICM
5. Voltage gain VG
R1
R1
EC1,
EC2
R2
VCC R2
-
VCC
+
VEE
+
NULL
-
VF5,VF6
VEE C
CMR = 20 log
(EC1 - EC2) (1+R2/R1)
VF5 - VF6
R1
R1
R2
VCC R2
-
VCC
+
RL
+
NULL
-
EK1, VEE
EK2
VG =
(EK1 - EK2) (1+R2/R1)
VF8 - VF7
VF7,VF8
C
6. Supply voltage rejection ratio SVR
R1
R1
R2
VCC1, R2
- VCC2
VCC
+
VEE
+
NULL
-
VF9,VF10
VEE C
SVR (+) = 20 log
(1+R2/R1) (VCC1 - VCC2)
VF9 - VF10
R1
R1
R2
VCC R2
-
VCC
+
VEE1,
VEE2
+
NULL
-
VEE
VF11,VF12
C
SVR (-) = 20 log
(1+R2/R1) (VEE1 - VEE2)
VF11 - VF12
7. Channel separation CS
a
R1
b
C VCC/2 VCC/2
b
R1
a
VIN VCC/2 VCC/2
R2
VCC
-
A
+
RL
R2
A VO
VCC
B
-
B
+
RL
SW: a
CS (A
B) = 20 log
R2 VOA
R1 VOB
SW: b
CS (B
A) = 20 log
R2 VOB
R1 VOA
These apply also to other channels.
No.2704-3/5
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