FM24CL64B(2014) Ver la hoja de datos (PDF) - Cypress Semiconductor
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FM24CL64B Datasheet PDF : 19 Pages
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FM24CL64B
Overview
The FM24CL64B is a serial F-RAM memory. The memory array
is logically organized as 8,192 × 8 bits and is accessed using an
industry-standard I2C interface. The functional operation of the
F-RAM is similar to serial (I2C) EEPROM. The major difference
between the FM24CL64B and a serial (I2C) EEPROM with the
same pinout is the F-RAM's superior write performance, high
endurance, and low power consumption.
Memory Architecture
When accessing the FM24CL64B, the user addresses 8K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the I2C
protocol, which includes a slave address (to distinguish other
non-memory devices) and a two-byte address. The upper 3 bits
of the address range are 'don't care' values. The complete
address of 13 bits specifies each byte address uniquely.
The access time for the memory operation is essentially zero,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the I2C bus. Unlike a
serial (I2C) EEPROM, it is not necessary to poll the device for a
ready condition because writes occur at bus speed. By the time
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
interface section.
I2C Interface
The FM24CL64B employs a bi-directional I2C bus protocol using
few pins or board space. Figure 3 illustrates a typical system
configuration using the FM24CL64B in a microcontroller-based
system. The industry standard I2C bus is familiar to many users
but is described in this section.
By convention, any device that is sending data onto the bus is
the transmitter while the target device for this data is the receiver.
The device that is controlling the bus is the master. The master
is responsible for generating the clock signal for all operations.
Any device on the bus that is being controlled is a slave. The
FM24CL64B is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge. Figure 4 and Figure 5 illustrates the
signal conditions that specify the four states. Detailed timing
diagrams are shown in the electrical specifications section.
Figure 3. System Configuration using Serial (I2C) nvSRAM
VDD
RPmin = (VDD - VOLmax) / IOL
RPmax = tr / (0.8473 * Cb)
Microcontroller
SDA
SCL
A0
SCL
A1
SDA
A2
WP
VDD
A0
A1
A2
SCL
SDA
WP
VDD
A0
SCL
A1
SDA
A2
WP
#0
STOP Condition (P)
A STOP condition is indicated when the bus master drives SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24CL64B should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of SDA in order to
assert a STOP condition.
#1
#7
START Condition (S)
A START condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the START condition will ready
the FM24CL64B for a new operation.
If during operation the power supply drops below the specified
VDD minimum, the system should issue a START condition prior
to performing another operation.
Document Number: 001-84458 Rev. *D
Page 4 of 19
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